This invention relates generally to buses that provide communication between electronic devices.
The speed at which data may be transmitted may have a significant impact on the performance of a system. Many improvements have recently been made in this field to achieve higher transmission rates. For instance, devices within a system typically transmit data through a shared parallel bus architecture, in which transmission of data by one device may slow down data transmission by other devices. A point-to-point high speed serial switching connection has been proposed as a possible solution to this problem. Such a connection may allow each device to have a dedicated link, without the need to obtain access to a shared bus. Moreover, a dedicated link may include multiple serial lanes, through which data may be transmitted in parallel.
However, while the lanes of the dedicated link typically transmit symbols simultaneously, a difference in the arrival time may occur at the receiver, for example. The arrival time difference is referred to as lane-to-lane skew. Sources of lane-to-lane skew may be chip input/output (“I/O”) drivers and receivers, printed wiring boards, electrical and optical cables, serialization and de-serialization logic, and/or retiming repeaters, for example. The lane-to-lane skew may include components that are less or equal to a bit time unit (i.e., the time needed to transmit a single bit) or a part or full symbol time unit (i.e., the time needed to transmit a symbol, generally including multiple bits) of skew. De-skew mechanisms may be implemented to ensure that data passes along in the correct order to higher layers.
While such de-skew mechanisms have worked well to reduce lane-to-lane skew, storing sequences until sequences in all lanes have advanced fully through the respective buffers creates a gap in the continuous data flow. Thus, there is a need for an improved way of reducing lane-to-lane skew.